mAbassi SMP RTOS for Cortex-A9

Multicore Ready

With a simple recompile, get automatic, multicore SMP, in less than 6 kilobytes.

And, in addition to the standard feature set supported by most real-time kernels, the Abassi RTOS can be configured with many features unmatched in the industry. These features add robustness and code savings, and include:


    1. Intelligent starvation protectionGuarantees fair access to CPU, via enhanced priority aging, even on heavily loaded systems.
    2. Priority inheritance, including dynamic trackingAutomatically adjusts for priority aging, timeouts, etc. and propagationBetween entangled mutex owners, to prevent deadlock.
    3. Adaptive priority ceiling
    4. Deadlock detectionReports recursive mutex dependencies anywhere in the execution chain.
    5. AsymmetricTimeslice adjustable at a per task level. Round Robin scheduling

Get Up And Running For Free

Download the freeware version of our multicore RTOS. Everything you need to get your multicore environment up and running and ready for real work.

Demonstration Package

Download an evaluation version of the RTOS, including demonstrations for multiple evaluation platforms. Full support for Altera Cyclone V, Altera Arria 10, Altera Arria V, Freescale i.MX6, Xilinx Zynq-7000, and TI OMAP4430 and OMAP4460.

Development Tool Choices

Abassi supports major ARM development tools, including ARM Design Studio 5, Xilinx SDK, Atollic TrueSTUDIO and Code Composer Studio.

Memory Requirements

Don't settle for half a RTOS! Even with all features enabled, Abassi still consumes less memory than the minimum configuration of most kernels. And you get advanced priority inheritance, asymmetric round-robin scheduling, starvation protection, and much more. Or, if memory footprint is paramount, Abassi scales to a minimum size that can't be matched.

"C" Code Memory Usage
Description Size
Minimal Build <1375 bytes
+ Runtime service creation / static memory <1650 bytes
+ Multiple tasks at same priority <2150 bytes
+ Runtime priority change
+ Mutex priority inheritance
+ FCFS
+ Task suspension
<2550 bytes
+ Timer & timeout
+ Timer call back
+ Round robin
<2925 bytes
+ Events
+ Mailbox
<3550 bytes
Full Feature Build (no name / no runtime creation) <3775 bytes
Full Feature Build (no names) <4175 bytes
Assembly Code Memory Usage
Description Size
Assembly code size (non-privileged / >1 core) 1588 bytes
Assembly code size (non-privileged / ==1 core) 1088 bytes
Assembly code size (privileged / >1 core) 1436 bytes
Assembly code size (privileged / ==1 core) 952 bytes
VFPv3 +128 bytes
VFPv3D16 +116 bytes
Saturation Bit Enabled +36 bytes
GICinit() 136 bytes
GICenable() 104 bytes

For your exact data memory requirements, please consult the Porting Document that applies to your design environment.

Kernel Snapshot

  1. Symmetric Multiprocessing
  2. Single core configurable
  3. Fully preemptive
  4. Scalable
  5. Very small code and data footprint
  6. Code can reside in ROM
  7. Zero interrupt latency kernel
  8. Mutexes
    1. Configurable priority inheritance
    2. Adaptive priority ceiling
    3. Priority based and first-come, first-served
  9. Versatile semaphores
    1. Counting and binary
    2. Priority based and first-come, first-served
  10. Mailboxes
    1. Priority based and first-come, first-served
  11. Events
  12. Intelligent starvation protection
  13. Deadlock detection
  14. Configurable Round Robin
  15. Dynamic priority changes
  16. Compile time task and component creation
  17. Run-time safe service creation
  18. No fixed number of tasks or components
  19. Programmable timeout on components
  20. Selectable scheduling search algorithm
  21. Debug logging