| Unlimited number of cores |
✔ |
✔ |
✔ |
✔ |
| True and packed SMP or BMP load balancing |
✔ |
✔ |
✔ |
✔ |
| Zero overhead interrupt segmentation |
✔ |
✔ |
✔ |
✔ |
| Simple interrupt handler attachment |
✔ |
✔ |
✔ |
✔ |
| All components available in interrupts |
✔ |
✔ |
✔ |
✔ |
| Portable source code |
✔ |
✔ |
|
|
| Mailboxes |
✔ |
Emulation |
✔ |
Reqst § |
| Events |
✔ |
Emulation |
✔ |
Reqst § |
| Cache initialization (L1/L2, SCU and MMU) |
✔ |
✔ |
✔ |
✔ |
| BSP (ie. EMAC, SDMMC, QSPI, ...) |
✔ |
✔ |
Reqst § |
Reqst § |
| Library reentrance / multithreading protection |
✔ |
✔ |
|
|
| Mutex deadlock detection |
✔ |
|
✔ |
|
| Mutex priority inversion protection |
✔ |
|
✔ |
|
| Symmetric and asymmetric round-robin |
✔ |
|
✔ |
|
| Starvation protection |
✔ |
|
✔ |
|
| Timer services |
✔ |
|
✔ |
|
| Memory block management |
✔ |
|
|
|
| Grouping |
✔ |
|
✔ |
|
| Wait abort |
✔ |
|
✔ |
|
| Performance monitoring |
✔ |
|
|
|
| Stack usage monitoring |
✔ |
|
✔ |
|
| Debugging log facilities |
✔ |
|
|
|
| ... And many more |
|
|
|
|
