mAbassi SMP RTOS for Cortex-A53

- 64 bit Multicore in than 10 kilobytes
- Sub micro-second RTOS services

In addition to the standard features supported by all RTOS, the Abassi family has many f eatures unmatched in the industry:


    1. Intelligent starvation protectionGuarantees fair access to CPU, via enhanced priority aging, even on heavily loaded systems.
    2. Priority inheritance, including dynamic trackingAutomatically adjusts for priority aging, timeouts, etc. and propagationBetween entangled mutex owners, to prevent deadlock.
    3. Adaptive priority ceilingTarget priority is self determined.
    4. Deadlock detectionReports recursive mutex dependencies anywhere in the execution chain.
    5. AsymmetricTimeslice adjustable at a per task level. Round Robin scheduling
    6. and more...

Get Up And Running For Free

Download the freeware version of our multicore RTOS. Everything you need to get your multicore environment up and running and ready for real work.

Development Tool Choices

Abassi supports major ARM development tools, including ARM Design Studio 5 and Xilinx SDK.

Memory Requirements

Don't settle for half a RTOS! Even with all features enabled, Abassi still consumes less memory than the minimum configuration of most kernels. And you get advanced priority inheritance, asymmetric round-robin scheduling, starvation protection, and much more. Or, if memory footprint is paramount, Abassi scales to a minimum size that can't be matched.

"C" Code Memory Usage
Description Size
Minimal Build <2550 bytes
+ Runtime service creation / static memory <3075 bytes
+ Runtime priority change
+ Mutex priority inheritance
+ FCFS
+ Task suspension
<3750 bytes
+ Timer & timeout
+ Timer call back
+ Round robin
<4850 bytes
+ Events
+ Mailbox
<6450 bytes
Full Feature Build (no name / no runtime creation) <6775 bytes
Full Feature Build (no names) <7525 bytes
Assembly Code Memory Usage
Description Size
Assembly code size (>1 core) 2116 bytes
Assembly code size (==1 core) 1512 bytes
Vector table 1972 bytes
Saturation Bit Enabled +24 bytes
GICinit() 196 bytes
GICenable() 400 bytes
Cache BSP 1604 bytes

For your exact data memory requirements, please consult the Porting Document that applies to your design environment.